Recent expanding of the scale of Large Scale Integrations (LSIs) and development of multi-core processors have increased the number of gates and internal signal lines and have consequently increased the number of faults needs to be detected. For the above, the time for testing using an LSI tester and the number of test patterns to be stored in the LSI tester increase to raise the cost for testing. Since the cost for testing increases in proportional to the number of test patterns, various techniques of reducing the number of test patterns have been proposed.
An example of such a technique of reducing the number of test patterns reduces the number of Automatic Test Pattern Generator (ATPG) patterns by inserting test points to an LSI having a full-scan system (see following Non-Patent Literature 1).
Here, a test point is a logic circuit for test controlling that is to be placed into a circuit to be tested, aiming at improving controllability and observability of a signal line in the circuit.
[Non-Patent Literature 1] M. Yoshimura, et al. “A Test Point Insertion Method to Reduce the Number of Test Patterns”, Proceedings of the 11th Asian Test Symposium (ATS'02) 2002 IEEE, pp 298-304
Here, the term “controllability” is an index set for each signal line or each terminal (pin) included in a circuit to be tested, and corresponds to the minimum number of signal lines for which logical values are to be set in order to set the values of the signal line and the pin to 0 or 1. The term “observability” is an index set for each signal line or each terminal (pin) included in a circuit to be tested, and corresponds to the minimum number of signal lines for which logical values are to be set in order to propagate a signal to an observation point. The term “observation point” is a point in a circuit to be tested at which the value of the point can be observed, and specifically corresponds to an output pin or a scan FF (Flip-Flop). The term “diagnosis difficulty index” is an index representing the difficulty in fault diagnosis at an observation point included in a circuit to be tested, and is used to find a signal line or a terminal that would be a bottleneck in reducing the number of test patterns.
A test point is a logical circuit that functions as a control point such as an AND gate or an observation point such as an output pin. The term “control point” is a point in a circuit to be tested at which the value of the point can be set, and is exemplified by a combination circuit including, for example, an AND gate and an OR gate that sets the value of a signal line to 0 or 1, and an input pin and a scan FF. Hereinafter, the term “test point” is sometimes abbreviated to “TP”. Inserting a TP into an internal signal line in a circuit to be tested for the improvement in testability, that is, in facilitating of generation of a test pattern, is sometimes referred to as Test Point Insertion, which may be abbreviated to “TPI”.
The above technique focuses on the fact that the presence of an observation point on which faults are concentrated increases the number of test patterns. The above technique determines a signal line which has the smallest maximum value of the diagnosis difficulty index among the diagnosis difficulty indexes at all the observation points in a circuit to be tested to a point onto which a TP is inserted, the signal line being one among the signal lines included in a circuit net (i.e., a logic cone) the vertex of which has the maximum value of the diagnosis difficulty index among all the observation points in the circuit. At that time, diagnosis difficulty indexes (e.g., a ratio of faults observed at each observation point) are defined and calculated using the scales of the 0/1 controllability and the observability, and a point onto which a TP is to be inserted is determined on the basis of the calculated diagnosis difficulty indexes. The above circuit net corresponds to a circuit net inside a logic cone obtained by back-tracing the signal lines from the vertex (i.e., the observation point having the maximum diagnosis difficulty index) to an input point or a control point.
However, the above technique evaluates signal lines having a possibility of being inserted a TP thereto and determines a signal line onto which a TP is to be inserted on the basis of the maximum diagnosis difficulty index among those of all the observation point of a circuit to be tested. For the above, if there are multiple logic cones the vertices of which have the maximum or the substantially maximum diagnosis difficulty index, it is impossible to select an optimum signal line in a desired logic cone to be a TPI point where TP is to be inserted in order to reduce the number of test patterns. In addition, there is a possibility of, if a TP is inserted into a logic cone, adversely affecting the diagnosis difficulty indexes of observation points in the remaining logic cones, which consequently would not successfully reduce the number of test patterns. In other words, if the diagnosis difficulty indexes of all the observation points after a TP is inserted (TPI) have large dispersion, the number of test patterns is not efficiently reduced.